Delta-sigma modulators with improved noise performance

ABSTRACT

An integrator stage for use in a delta sigma modulator includes an operational amplifier, an integration capacitor coupling an output of the operational amplifier and a summing node at an input of the operational amplifier, and a feedback path. The feedback path includes first and second capacitors having first plates coupled electrically in common at a common plate node and switching circuitry for sampling selected reference voltages onto second plates of the capacitors during a sampling phase. The integrator stage further includes a switch for selectively coupling the common plate node and the summing node during an integration phase.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates in general to switched-capacitortechniques and in particular to delta-sigma modulators with improvednoise performance.

[0003] 2. Description of Related Art

[0004] Delta-sigma modulators are particularly useful in digital toanalog and analog to digital converters (DACs and ADCs). Usingoversampling, the delta-sigma modulator spreads the quantization noisepower across the oversampling frequency band, which is typically muchgreater than the input signal bandwidth. Additionally, the delta sigmamodulator performs noise shaping by acting as a lowpass filter to theinput signal and a highpass filter to the noise; most of thequantization noise power is thereby shifted out of the signal band.

[0005] The typical delta sigma modulator includes a summer summing theinput signal with negative feedback, a linear filter, quantizer and afeedback loop with a digital to analog converter coupling the quantizeroutput and the inverting input of the summer. In a first ordermodulator, the linear filter comprises a single integrator stage whilethe filter in a higher order modulator comprises a cascade of acorresponding number of integrator stages. The quantizer can be either aone-bit or a multiple-bit quantizer. Higher-order modulators haveimproved quantization noise transfer characteristics over those of lowerorder, but stability becomes a more critical design factor as the orderincreases.

[0006] Switched-capacitor filters/integrators are useful in a number ofapplications including the integrator stages in delta sigma modulators.Generally, a basic differential switched-capacitor integrator samplesthe input signal onto sampling capacitors during the sampling (charging)phase. A reference voltage may also be sampled onto a reference samplingcapacitors during this phase. During the following dump phase, thecharge on the sampling capacitor is transferred at the summing node ofan operational amplifier to the integrator capacitor in the amplifierfeedback loop. The operational amplifier drives the integrator output.

[0007] Noise performance is an important design constraint indelta-sigma modulator development. Noise can result from a number ofdifferent factors, including parasitic capacitances and timingmismatches. Hence, for applications requiring low-noise delta-sigmamodulation, improved techniques for reducing noise are required.

SUMMARY OF THE INVENTION

[0008] Circuits and methods according to the inventive principles areparticularly useful in improving the performance of delta sigmamodulators, such as those used in digital to analog and analog todigital converters. a corresponding capacitor during a sampling phase.According to one particular embodiment, an integrator stage is disclosedfor use in a delta sigma modulator includes an operational amplifier, anintegration capacitor coupling an output of the operational amplifierand a summing node at an input of the operational amplifier, and afeedback path. The feedback path includes first and second capacitorshaving first plates coupled electrically in common at a common platenode and switching circuitry for sampling selected reference voltagesonto second plates of the capacitors during a sampling phase. Theintegrator stage further includes a switch for selectively coupling thecommon plate node and the summing node during an integration phase.

[0009] Among the many advantages afforded by the application of theinventive concepts are improved noise performance and a relaxation inthe design constraints on the modulator integrator stages. By isolatingthe reference path feedback switches from the summing nodes duringsampling, non-linearities caused by parasitic capacitances of thoseswitches can be avoided. Additionally, techniques are disclosed forimplementing signal energy cancellation within the delta-sigma loopthereby reducing the in-loop noise to small amounts of quantizationnoise.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] For a more complete understanding of the present invention, andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawings, inwhich:

[0011]FIG. 1 is a high level functional block diagram of an analog todigital converter suitable for illustrating the application of theinventive principles;

[0012]FIG. 2 is a functional block diagram of an exemplary 5^(th) orderdelta-sigma modulator suitable for use in circuits and systems such asthe analog to digital converter shown in FIG. 1;

[0013]FIG. 3A is a more detailed functional block diagram of the firstintegrator stage and integral multiple-bit DAC shown in FIG. 2;

[0014]FIG. 3B is a more detailed functional block diagram of theintegral multiple-bit DAC shown in FIG. 3A;

[0015]FIG. 3C is a conceptual diagram of one of the switches of FIG. 3Bshowing representative parasitic capacitances; and

[0016]FIG. 4 is a timing diagram illustrating the operation of thedelta-sigma modulator of FIG. 2.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] The principles of the present invention and their advantages arebest understood by referring to the illustrated embodiment depicted inFIG. 1-4 of the drawings in which like numbers designate like parts.

[0018]FIG. 1 is a high-level functional block diagram of a single-chipaudio analog-to-digital (A/D) 100 suitable for practicing the principlesof the present invention. A/D converter 100 is only one of a number ofpossible applications employing delta-sigma data converters. Otherexamples include digital to analog converters (DACs) and Codecs.

[0019] A/D converter 100 includes two conversion paths for convertingleft and right channel analog audio data respectively received at leftand right analog differential inputs AINL+/− and AINR+/−. The analoginputs are each passed through an input gain stage 101 a-101 b and thento a delta—sigma analog to a digital converter (ADC) 200 a-200 b, whichwill be described in detail in conjunction with FIG. 2. The digitaloutputs of delta-sigma ADCs 200 a-200 b are passed through a decimationfilter 107, which reduces the sample rate, and a low pass filter 108.Delta sigma ADCs 200 a-200 b sample the analog signal at theoversampling rate and output digital data, in either single-bit ormultiple-bit form depending on the quantization, at the oversamplingrate. The resulting quantization noise is shaped and generally shiftedto frequencies above the audio band.

[0020] The resulting left and right channel digital audio data areoutput through a single serial port SDOUT of serial output interface109, timed with serial clock SCLK and left-right clock LRCLK inaccordance with the Digital Interface Format (DIF). The SCLK and LRCLKclocks can be generated externally and input to converter 100 or can begenerated on-chip, along with the associated data, in response to areceived master clock MCLK.

[0021]FIG. 2 is an exemplary 5th order delta-sigma modulator 200comprising an input summer 201 and five (5) integrator stages 202 a-202e. Delta sigma modulator 200 is a weighted feed-forward design in whichthe outputs of each of the integrator stages are passed through a gainstage (amplifier) 203 a-203 e to an output summer 204. Amplifiers 203a-203 e allow the outputs of the integrator stages to be weighted at thesummer 204 input. The output from summer 204 is quantized by amultiple-bit quantizer 205, which generates the multiple-bit digitaloutput signal. Additionally, the output from quantizer 205 is fedback tothe inverting input of summer 201 through dynamic element matching (DEM)circuitry 206 and multiple-bit digital to analog converter (DAC) 207. (A5th order feed-forward design was selected for discussion purposes; inactual implementation; the order as well as the configuration of themodulator will vary. A general discussion of delta-sigma modulatortopologies can be found in the literature, for example, in Norsworthy etal., Delta-Sigma Data Converters, Theory, Design and Simulation, IEEEPress, 1996).

[0022]FIG. 2 also shows an additional feed-forward path, includingamplifier 208, between modulator input 210 and summer 204. The gain ofamplifier stage 208 is preferably:

Gain=(1/Quantizer gain)*(1/Multi-Bit DAC gain)

[0023] The purpose of this additional feed-forward path is to cancel asmuch of the input signal energy from the delta-sigma loop as possible.Consequently, most of the noise within the modulator will bequantization noise. In turn, the design constraints on the sub-circuitswithin modulator 200 can be relaxed. For example, the first integratorstage 202 a is typically the major contributor to the noise performanceof the entire modulator. This feed-forward technique results in lesssignal energy at the output of the first integrator stage and hence suchparameters as the stage opamp DC gain can be reduced. In turn, the powerconsumption of the device as well as the die size can be reduced.

[0024]FIG. 3A is an electrical schematic diagram of an integralswitched-capacitor summer—DAC—integrator circuit 300 corresponding tofirst integrator stage 202 a, summer 204 and DAC 207 of delta sigmamodulator 200. Generally, the design of the first integrator stage of adelta-sigma modulator is the most critical to setting the distortionperformance and therefore will be the focus of the following discussion.However the concepts discussed below are useful in a number of switchedcapacitor applications, including various delayed and undelayed switchedcapacitor integrators.

[0025] Switched capacitor integrator 300 generally operates in twonon-overlapping Phases φ₁ and φ₂. The timing of Phases φ₁ and φ₂ isshown in FIG. 4. Delayed Phases φ_(1d) and φ_(2d) are delayed versionsof Phases φ₁ and φ₂. As will be discussed further, in the preferredembodiment each delayed phase is composed of rough (R) and fine (F)subphases (Subphases φ_(1dR), φ_(1dF), φ_(2dR), φ_(2dF)). Additionally,in the illustrated embodiment, a double sampling technique is utilizedto sample the input signal V_(IN) and/or the reference signal V_(REF).For double sampling, the input plate of the each sampling capacitor iscoupled to either V_(IN) or V_(REF) during φ₁ sampling with a givenpolarity. During φ₂ integration, the charge on each sampling capacitorinput plate is then forced to the opposite plate by reversing thepolarity of the corresponding voltage at that input plate.

[0026] In the general case, switches 304 a-304 b close during Phase φ₁During Delayed Phase φ_(1d) switches 301 a-301 d and 304 a-304 b closeand the differential input voltage V_(IN) is sampled onto input samplingcapacitors (C_(IN)) 303 a-303 b. Switches 302 a-302 d and 305 a-305 bare open during Phase φ₁.

[0027] Also during Phase φ₁ the reference voltage is sampled by DAC 207for presentation to summing nodes A and B. Two data paths of an n-bitDAC operating in response to digital bits and their complements (D and/D) from DEM circuitry 206 are shown in further detail FIG. 3B forreference.

[0028] Generally during Phase φ₁, the differential reference signalV_(REF) is sampled onto reference sampling capacitors (C_(REF)) 306a-306 b for each path by switches 307 a-307 d and 304 a-304 b (FIG. 3A).Switches 309 a-309 d (FIG. 3A) are open during Phase φ₁. Switches 310a-310 d for each path, under the control of complementary bits Dx and/Dx, couple or cross-couple the input plates of reference samplingcapacitors C_(REF) 306 a-306 b to the common plate (charge sharing)nodes A and B (where x is the index for the corresponding bit/referencesampling path from 0 to n from the quantizer and DEM circuitry). Inother words, the configuration of switches 310 a-310 d for a givenreference sampling path sets the polarity of the voltage at the inputplates of capacitors 306 a-306 b.

[0029] During Phase φ₂ the sampling switches reverse their configurationwith switches 302 a-302 d closing and switches 301 a-301 d and 304 a-304d opening for the input signal path. For the reference path, switches307 a-307 d open and switches 309 a-309 d close. The charge on the inputplates of capacitors C_(IN) and C_(REF) is forced to the output (top)plates and common plate (charge sharing) nodes A and B. During DelayedPhase φ_(2d) switches 305 a-305 b close to transfer the charge at commonnodes A and B from the top plates of reference sampling capacitorsC_(IN) and C_(REF) to the the summing nodes at the inverting (−) andnon-inverting (+) inputs of opamp 312 (the summing nodes) and integratorcapacitors (C_(I)) 313 a-313 b.

[0030] As previously noted, the preferred integrator 300 operates inrough and fine subphases. During Rough Delayed Subphase φ_(1dR), theinput plates of sampling capacitors C_(IN) and C_(REF) are driven byrough buffers 314 a-314 d and 315 a-315 d which provide an increasedcharging current. Subsequently, input plates P are brought to their fullsampling voltage during Delayed Fine Subphase φ_(1dF) by direct couplingto the corresponding input or reference voltage. More importantly, roughbuffers 314 and 315 provide increased drive during Rough DelayedSubphase φ_(2dR) to rapidly slew the voltage on capacitor input plates Ptowards the opposite voltage to transfer the sampled charge to the topplates P′ and integration capacitors C_(I). The charge transfer iscompleted during Delayed Fine Subphase φ_(2dF) by direct coupling of theinput and reference capacitor (C_(IN) and C_(REF)) input plates P to theappropriate input.

[0031] According to the inventive concepts, DAC switches 310 aredisposed in front of reference capacitor 306 of each reference path. Inother words, switch 310 switches the charge at the input plates P ofcapacitors C_(REF). This is in contrast to conventional designs in whichthe charge summing is done at output or top plates P′.

[0032] With switches 310 disposed in front of reference capacitorsC_(REF), the top plates of corresponding reference capacitors 306 a and306 b is preferably either fabricated in common or tied together. Thisfeature is shown generally in FIG. 3B by lines 311 a-311 b represent thecommonality of all top plates P′ of reference capacitors 306 a (lines311 a) and the commonality of all top plates P′ of reference capacitors306 b (lines 311 b).

[0033]FIG. 3C is a conceptual schematic diagram of one switch 310illustrating the gate—source parasitic capacitance C_(GS) and thegate—drain parasitic capacitance C_(GD). Control signals Dx and /Dx,coming from the quantizer 205 and DEM 206 circuitry, are independent ofthe modulator input signal. Hence, when switches 310 turn on and off,parasitic capacitances C_(GS) and C_(GD) charge and dischargeindependent of the input signal. If this charge were to be coupled intothe integration capacitors C_(I), non-linearities would appear in theopamp 312 output and consequently in the entire system in general. Withthe configuration of FIG. 3B however, switches 310 are isolated from thesumming nodes A and B such that non-linearities are not introduced bythe parasitic capacitances of switches 310.

[0034] The configuration of switches 310 by control signals Dx and /Dxis set before the start of the current φ₁. In order for this “decision”to be made in sufficient time, control signals Dx and /Dx are preferablygenerated during φ₂ of the prior cycle. This timing allows Dx and /Dx topropagate from the quantizer 206 outputs and through DEM circuitry 207to switches 310 before the rising edge of Phase φ₁ of the current cycle.

[0035] One advantage of the configuration of FIG. 3B is its ability tocancel charge at the common plate (charge sharing) nodes A and B. In anideal delta-sigma modulator the input signal charge and feedback chargeat nodes A and B cancel such that only a small quantization noise chargeis transferred onto integration capacitors C_(I). In actual practicehowever, if the two charges do not reach the summing nodes at orapproximately the same time, then a large input signal or feedbacksignal charge will be transferred onto the integration capacitors. Ifthis event occurs, a large signal swing will appear at the opampoutputs.

[0036] In contrast to conventional modulator topologies, in modulator200 the input signal and feedback charges are summed at common nodes Aand B, which are disposed in front of summing switches 305.Consequently, during φ₁ the charges from the input and referencecapacitors and C_(IN) and C_(REF) are shared at Nodes A and B beforesumming switches 305 close and the charge is transfered to the summingnodes at the operational amplifier inputs. As indicated above, duringPhase φ₂ the charge from all paths are switched to charge sharing nodesA and B. This timing allows input and feedback charge from capacitorsC_(IN) and C_(REF) to cancel at nodes A and B such that only a smallquantization noise charge is transferred to the opamp inputs duringPhase 2 delayed (φ_(2d)) when switches 305 close.

[0037] Preferably, nodes A and B for the first integrator stage aredisconnected from the signal inputs V_(IN+) and V_(IN−) prior todisconnection of the signal feed-forward path. Moreover, the inputsignal feedforward path is preferably disconnected from the modulatorinputs shortly after the quantizer comparison operation. The advantageof taking these steps is the minimization of unwanted sampling ofsignals caused by descriptions of the feedforward path. Additionally,the feedforward path provides a possible link between the input signaland internal quantization noise. Hence attention must be paid to thedesign of the feedforward path to avoid possible dilution of the inputsignal.

[0038] Although the present invention and its advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

What is claimed is:
 1. An integrator stage for use in a delta sigmamodulator comprising: an operational amplifier; an integration capacitorcoupling an output of the operational amplifier and a summing node at aninput of the operational amplifier; first and second feedback paths eachincluding switching circuitry for selectively sampling a referencevoltage onto a first plate of a corresponding capacitor during asampling phase, a second plate of the capacitors of the feedback pathsbeing coupled in common at a common plate node; and a switch forselectively coupling the common plate node and the summing node duringan integration phase.
 2. The integrator stage of claim 1 and furthercomprising: a second integration capacitor coupling a second output ofthe operational amplifier with a second summing node at a second inputof the operational amplifier; third and fourth feedback paths eachincluding switching circuitry for selectively sampling the referencevoltage onto a first plate of a correponding capacitor during thesampling phase, a second plate of the capacitors of the third and fourthfeedback paths coupled in common at a second common plate node, thethird and fourth feedback paths sampling the reference voltagedifferentially with respects to the first and second feedback paths; anda second switch for selectively coupling the second common plate nodeand the second summing node during the integration phase.
 3. Theintegrator stage of claim 1 wherein the switching circuitry comprisesswitches for selectively coupling and cross-coupling first and secondreference voltage inputs of the corresponding feedback path in responseto a control signal.
 4. A delta sigma modulator comprising: a loopfilter comprising an integrator stage, the integrator stage comprising:an operational amplifier; an integration capacitor coupling an output ofthe operational amplifier and a summing node at an input of theoperational amplifier; and a mutiple-bit digital to analog convertercomprising: first and second capacitors having first plates coupled incommon at a common node; switching circuitry for selectively sampling aselected reference voltage onto a second plate of a corresponding one ofthe capacitors during a sampling phase; and switching circuitry forselectively coupling the common node with the summing node during anintegration phase.
 5. The delta sigma modulator of claim 4 furthercomprising: a output summer coupled to outputs of the loop filter in afeedforward configuration; and a feedforward path of a selected gaincoupling a loop filter input and the output summer for canceling aninput signal energy into the loop filter input.
 6. The delta sigmamodulator of claim 5 further comprising a quantizer for feeding-back acontrol signal to the switching circuitry of the digital to analogconverter, a gain of the feed-forward path inversely proportional togains of the quantizer and the digital to analog converter.
 7. A deltasigma modulator comprising: a plurality of filter stages having outputscoupled to inputs of an output summer; a feedback loop coupled to anoutput of the output summer and having a gain for feeding-back controlsignals to at least one of the filter stages; and a feed-forward pathcoupling an input of the modulator and an input of the output summer andhaving a gain approximately inversely proportional to the gain of thefeedback loop.
 8. The delta-sigma modulator of claim 7 wherein thefeedback loop comprises a quantizer and a DAC and the gain of thefeed-forward path is approximately: 1/quantizer gain*1/ DAC gain.
 9. Thedelta-sigma modulator of claim 7 wherein a selected one of the filterstages comprises an integrator stage comprising: an operationalamplifier and an associated integration capacitor; input signalswitching circuitry for sampling an input signal charge onto an inputsampling capacitor during a sampling phase and transferring the inputsignal charge to a common node during a first period of an integrationphase; reference voltage switching circuitry including switchescontrolled by a plurality of control signals generated by the feedbackloop for sampling a reference charge onto a plurality of referencesampling capacitors during the sampling phase and transferring thereference charge to the common node during the first period of theintegration phase; and summing switches for transferring charge from thecommon node to the integration capacitor during a second period of theintegration phase.
 10. The delta-sigma modulator of claim 9 whereinselected plates of selected ones of the plurality of reference samplingcapacitors are coupled electrically in common.
 11. The delta sigmamodulator of claim 8 further wherein the feedback loop further comprisesdynamic element matching logic coupling the quantizer and the DAC. 12.The delta sigma modulator of claim 9 wherein the switches of thereference voltage switching circuitry selectively couple the referencesampling capacitors to a selected one of first and second referencevoltage rails.
 13. The delta sigma modulator of claim 9 wherein theinput signal switching circuitry samples the input signal charge inrough and fine subphases of the sampling phase.
 14. The delta sigmamodulator of claim 9 wherein the reference voltage switching circuitrysamples the reference voltage in rough and fine subphases of thesampling phase.
 15. The delta sigma modulator of claim 9 wherein thecontrol signals are generated during the integration phase of a firstoperational cycle to configure the switches of the reference switchingcircuitry prior to the sampling phase of a second following operationalcycle.
 16. A method of operating a switched capacitor integratorcomprising the steps of: during a sampling phase selectively sampling areference voltage of a selected polarity onto an input plate of areference capacitor in response to a control signal; during the samplingphase selectively sampling an input signal voltage onto an inputsampling capacitor; during a first period of an integration phase,transferring the sampled voltages from the reference and input samplingcapacitors to a common node; and during a second period of theintegration phase, transferring the sampled voltages from the commonnode to an integration capacitor.
 17. The method of claim 16 furthercomprising the step of generating the control signal during anintegration phase preceding said step of sampling the reference voltage.18. A method of operating a delta-sigma modulator including a loopfilter having a plurality of outputs feeding-forward filter outputsignals into an output summer and a feedback loop for coupling afeedback signal from an output of the summer to an input of the loopfilter comprising the step of: feeding-forward an input signal through afeed-forward path from a modulator input to the output summer with aselected gain for canceling input signal energy into the modulator. 19.The method of claim 18 wherein said step of feeding-forward comprisesthe substeps of: disconnecting an input stage of the loop filter inputfrom the modulator input; and subsequently disconnecting thefeed-forward path from the modulator input.
 20. The method of claim 19,wherein the feed-forward path is disconnected after the feedback pathgenerates the feedback signal.
 21. A method of interconnecting paths andan integration capacitor in a switched-capacitor integrator comprisingthe steps of: coupling top plates of first and second referencecapacitors of first and second reference paths of a selected polaritytogether at a common node; and coupling a switch between the common nodeand the integration capacitor for selectively coupling the common nodeto the integration capacitor.
 22. The method of interconnecting of claim21 and further comprising the step of providing switches for selectivelycoupling input plates of the reference capacitors to a reference voltageof a selected polarity.
 23. The method of interconnecting of claim 21further comprising the step of coupling a top plate of an input signalsampling capacitor to the summing node.
 24. A method of operating adelta sigma modulator comprising a loop filter including an integratorstage, a quantizer, first and second capacitors having common firstplates, first switching circuitry for selectively sampling a selectedreference voltage to a second plate of the each of the capacitors inresponse to a control signal generated by the quantizer, and secondswitching circuitry for transfering charge from the common first platesof the capacitors to the input of the integrator stage, comprising thesteps of: during a first sampling phase, sampling selected referencevoltages to the second plates of the capacitors with the first switchingcircuitry in response to a first control signal generated by thequantizer during a prior integration phase; during a first integrationphase performing the substeps of: selectively transfering charge fromthe common first plates of the first and second capacitors to the inputof the integrator stage with the second switching circuitry; andgenerating a second control signal with the quantizer; and during asecond sampling phase, sampling selected reference voltages to thesecond plates of the capacitors with the first switching circuitry inresponse to the second control signal generated by the quantizer. 25.The method of claim 24 wherein said step of transferring charge from thefirst common plates of the capacitors to the input of the integratorstage comprises the step of transfering charge to a selected one offirst and second differential inputs to the integrator stage.
 26. Themethod of claim 25 and further comprising the step of passing the firstand second control signals generated by the quantizer through dynamicelement matching logic prior to presentation to the first switchingcircuitry.
 27. The method of claim 25 wherein said integration phasefurther comprises the step of forcing charge from the second plates ofthe capacitors to the common first plates of the capacitors by reversinga voltage at the second plates of the capacitors prior to said step ofselectively transferring charge from the common first plates to theinput of the integrator.